1. Field of the Invention
This invention relates to metal oxide semiconductor (MOS) fabrication and more particularly to an improved method for manufacturing an MOS device having drain-side implant regions which extend into the channel area.
2. Background of the Relevant Art
Recent advances in semiconductor fabrication have made possible ultra large scale integrated (ULSI) circuits with dense layout topography. As circuits become more dense, critical dimensions of the polysilicon gate area become extremely small. In many instances, circuits have been manufactured having gate lengths less than one micron, and in some instances less than one half micron.
It is important that critical dimensions be reduced in order for the monolithic circuit to accommodate as many active and passive devices as possible. It is also important to control the deleterious effects often associated with smaller critical dimensions. Smaller critical dimensions generally bring about what is often called "short channel effects". For example, as the channel length decreases a greater opportunity arises for electric field charge to invert the short channel area. As such, the effects of a shorter channel may cause significant reduction the MOS device's threshold voltage. Secondly, because of the short channel (i.e., close proximately between the source and drain region), some channel leakage might arise during times in which the transistor should be completely off. While all transistors demonstrate some form of leakage, subthreshold leakage associated with a short channel transistor can be quite large and lead to severe power drains upon the circuit power supply. Thirdly, the drain region may "punch through" to the closely spaced source region when relatively small voltages are placed upon the drain, relative to the source and substrate. The punch through phenomena, often referred to as "breakdown voltage" (BVDSS), is well documented and is particularly acute in short channel length transistors. The above problems are only a few of many problems associated with short channel effects, all of which are well known to the skilled artisan.
In an effort to overcome short channel effects, many researchers and semiconductor manufactures utilize a well known technique, called "large-angle implants". Large-angle implant (LAI) reduces or inhibits charge mobility between the source and drain regions and within the channel by implanting an impurity region partially within the channel of opposite impurity type than that of the source or drain. LAI requires the impurity species be directed at a non-perpendicular angle of approximately 45.degree. relative to the substrate upper surface. LAI occurs after the polysilicon is deposited and patterned, as shown in FIG. 14. LAI implant, of opposite impurity than source or drain regions 12 (i.e., the same impurity type as the substrate), can penetrate into substrate 10 a lateral distance, L, inside the outer edge of polysilicon 14.
LAI technique can perform channel implant from either the drain side, the source side, or both sides of an active MOS device. As shown in FIG. 14, LAI implant can occur from, e.g., only the drain-side provided the source side is masked off by photoresist 16. Placement of photoresist and selectively removing the portions of photoresist within the active area requires an additional masking step. Still further, LAI, due to its non-perpendicular orientation, requires a special implanter be placed at a unique angle relative to the substrate. Moreover, the substrate or implanter must be re-oriented each time a set of drains (or sources) 12 are to be implanted underneath a portion of polysilicon 14. As shown in FIG. 14, if drain-side implants are needed, the wafer must be re-oriented in relation to the implanter in order to implant both drain areas as shown. It may be necessary, in many instances, to re-orient the wafer at four different position in order to achieve all four possibilities of drain-side implant locations.
As shown in FIG. 15, a further problem associated with LAI techniques is demonstrated whenever the critical dimensions become extremely small. As critical dimensions become less than a specified amount (e.g., 0.5 microns), the angle of implantation may not allow implant underneath polysilicon 14 given the geometries of the overlying photoresist 16. Photoresist 16 over the source of one device may absorb the impurity species meant for placement within an adjacent device's drain.
The problems described above and shown in FIGS. 14 and 15 arise in all LAI techniques. Additional masking steps and patterned photoresist are necessary when implanting on only the source-side of the channel. Even if implanting in both the source and drain-sides is allowed, additional masking steps are nonetheless needed in order to block off or mask the N-channel devices from the P-channel devices in CMOS fabrication. Thus, masking steps and associated alignment problems as well as implanter or substrate re-orientation problems lessens the advantages of LAI in overcoming short channel problems described above.